The invention is concerned with the self-analysis and self-organization of an integrated circuit. The invention is particularly concerned with the testing and configuration of clusters of functionally-equivalent modules in an integrated circuit by a test and configuration architecture which is integrated into a common monolithic structure with the functionality clusters.
Development of fault-tolerant systems at the semiconductor level has many obstacles. No portion of a semiconductor can ever be guaranteed to be functional. The problem, therefore, in the fabrication, testing, and configuration of integrated circuits is the detection of failed devices and the substitution of other, operable devices for the failed ones. The ability to detect malfunctioning devices and to substitute spares which are in the same integrated monolithic circuit have the effect of increasing device yields. Devices which have been tested as operable can be interconnected with other, similarly tested devices which are in the same integrated circuit with the result that apparatus or system integration can occur at the wafer scale level.
Wafer scale integration requires architectural fault tolerance dependent upon effective testing and reconfiguration of component devices. To date, there have been two common approaches to fault diagnosis and recovery: centralized and distributed.
In a centralized scheme, the architecture of an apparatus or system whose components reside on a single chip typically incorporates a routing grid of all test points to a centralized I/0 port. This centralized port may perform some base processing; however, its primary function is to pass data from the individual devices on the chip to an external device. The external device is required to initiate device testing, provide test vectors to portions of the wafer using specialized test buses, and interconnect the wafer system to a specialized command bus. There are disadvantages to this structure. First, failure of the centralized device results in a complete failure of the system. By requiring all portions of a wafer to be exercised by an external portion, or by a single device, there is usually a restriction on the variations of testability within the system. This architecture is also disadvantageous in requiring external systems to exercise the wafer.
In a distributed scheme of self-testing and configuration, the functional portions of a wafer are responsible for performing periodic self-testing and reconfiguration based on nearest-neighbor data. This architecture uses the devices themselves in a very complicated and usually non-standard state machine structure. In distributed architectures, a large circuit increase is typical due to the increase in circuit complexity associated with nearest neighbor self-test. Distributed architectures are also not usually capable of removing devices associated with test from the main body of the data path. This results in a slower system overall simply due to the computational overhead associated with architectural distribution. These architectures also tend to be very inflexible due to the complexity of the state machines necessary to perform testing and reconfiguration. Distributed architectures typically find their primary application in integrated systems having highly regular structures. An example of a system with a regular structure is a semiconductor memory.